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SINGLE CHANNEL 0.7V DIFFERENTIALTO-LVTTL TRANSCEIVER
ICS8512061I Features
* * * * * * * * *
One HCSL output pair and one LVCMOS/LVTTL output One single-ended LVCMOS/LVTTL signal input LVTTL I/O signal: up to 250MHz HCSL interface pins in high impedance state when the device is powered down Power-up and power-down glitch-free Additive Phase Jitter, RMS: 0.23ps (typical) Full 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package
General Description
ICS
HiPerClockSTM
The ICS8512061I is a transceiver which can interchange data across multipoint data bus structures.
The device has an LVTTL driver and one HCSL receiver driver. It translates between LVTTL signals and HCSL signals.
Applications
Backplane Transmission Telecommunication System Data Communications ATCA Clock Distribution
Block Diagram
Pin Assignment
GND QB DIR_SEL IN 1 2 3 4 8 7 6 5 QA nQA VDD IREF
QB
IREF
HCSL Interface QA
ICS8512061I 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
IN
Pullup
nQA DIR_SEL Pulldown
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Table 1. Pin Descriptions
Number 1 2 3 4 5 6 7, 8 Name GND QB DIR_SEL IN IREF VDD nQA, QA Power Output Input Input Input Power Output Pulldown Pullup Type Description Power supply ground. Single-ended output. LVCMOS/LVTTL interface levels. HCSL receiver and driver direction select pin. When HIGH, selects the IN-to-QA/nQA path. When LOW, selects the QA/nQA-to-QB path. LVCMOS/LVTTL interface levels. Single-ended signal input. LVCMOS/LVTTL interface levels. An external fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode QA/nQA outputs. Power supply pin. Differential transceiver pair. HCSL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Input Pullup Resistor Input Pulldown Resistor Output Impedance QB VDD = 3.6V Test Conditions Minimum Typical 4 8 51 51 20 Maximum Units pF pF k k
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 129.5C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V 0.3V, TA = -40C to 85C
Symbol VDD IDD Parameter Core Supply Voltage Power Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 3.6 20 Units V mA
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Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 0.3V, TA = -40C to 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage IN Input High Current DIR_SEL IN IIL VOH VOL Input Low Current DIR_SEL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 QB QB VDD = VIN = 3.6V VDD = VIN = 3.6V VDD = 3.6V, VIN = 0V VDD = 3.6V, VIN = 0V VDD = 3.6V VDD = 3.6V -150 -5 2.6 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V A A A A V V
NOTE: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information Section, Output Load Test Circuit diagram.
Table 3C. Differential DC Characteristics, VDD = 3.3V 0.3V, TA = -40C to 85C
Symbol VPP VCMR Parameter Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions DIR_SEL = 0 DIR_SEL = 0 Minimum 0.15 GND + 0.5 Typical Maximum 1.3 VDD - 0.85 Units V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH.
AC Electrical Characteristics
Table 4A. LVTTL (QB) Output Mode, Receiver AC Characteristics, VDD = 3.3V 0.3V, TA = -40C to 85C
Symbol FMAX tPD tjit tR/tF odc Parameter Output Frequency Propagation Delay, NOTE 1 Buffer Additive Phase Jitter, RMS Output Rise/Fall Time Output Duty Cycle QA/nQA to QB 100MHz, Integration Range: 12kHz - 20MHz 20% - 80% 200 40 1.7 0.23 700 60 Test Conditions Minimum Typical Maximum 250 2.5 Units MHz ns ps ps %
NOTE 1: Measured from VDD/2 input cross point to the output at VDD/2.
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Table 4B. HCSL (QA/nQA) AC Characteristics, VDD = 3.3V 0.3V, TA = -40C to 85C
Parameter fMAX tjit tPD Rise Edge Rate Fall Edge Rate Vrb VMAX VMIN VCROSS VCROSS odc Symbol Output Frequency Buffer Additive Phase Jitter, RMS Propagation Delay, NOTE 1 Rising Edge Rate; NOTE 2, 3 Falling Edge Rate; NOTE 2, 3 Ringback Voltage; NOTE 2, 4 Absolute Max Output Voltage; NOTE 5, 6 Absolute Min Output Voltage; NOTE 5, 7 Absolute Crossing Voltage; NOTE 5, 8, 9 Total Variation of VCROSS over all edges; NOTE 5, 8, 10 Output Duty Cycle; NOTE 11 45 -300 250 550 140 55 100MHz, Integration Range: 12kHz - 20MHz IN to QA/nQA 1.1 0.6 0.6 -100 0.29 1.7 4.0 4.0 100 1150 Test Conditions Minimum Typical Maximum 250 Units MHz ps ns V/ns V/ns V mV mV mV mV %
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 input cross point to the differential output crossing point. NOTE 2: Measurement taken from differential waveform. NOTE 3: Measurement from -150mV to +150mV on the differential waveform (derived from QA minus nQA). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. NOTE 4: TSTABLE is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB 100 differential range. See Parameter Measurement Information Section. NOTE 5: Measurement taken from single-ended waveform. NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of QA equals the Falling edge of nQA. See Parameter Measurement Information Section NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 10: Defined as the total variation of all crossing voltage of Rising QA and Falling nQA. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section. NOTE 11: Input duty cycle must be 50%.
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Additive Phase Jitter (HCSL)
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 100MHz 12kHz to 20MHz = 0.29ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
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Additive Phase Jitter (LVCMOS)
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 100MHz 12kHz to 20MHz = 0.23ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
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Parameter Measurement Information
3.3V0.3V
1.65V0.15V VDD
33 49.9
50
Qx
VDD
SCOPE
Qx
HCSL
IREF GND 475 33 49.9 50
2pF nQx 2pF
LVCMOS
GND
0V
-1.65V0.15V
3.3V HCSL Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
nQA
VDD
IN nQA QA
QA
2 VDD 2 t
QB
PD
tPD
Differential Propagation Delay
LVCMOS Propagation Delay
TSTABLE
Rise Edge Rate Fall Edge Rate
VRB
+150mV VRB = +100mV 0.0V VRB = -100mV -150mV
+150mV 0.0V -150mV Q - nQ
Q - nQ VRB TSTABLE
Differential Measurement Points for Rise/Fall Time
Differential Measurement Points for Ringback
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Parameter Measurement Information, continued
Clock Period (Differential) nQ Positive Duty Cycle (Differential) Negative Duty Cycle (Differential)
VCROSS_DELTA = 140mV 0.0V Q Q/nQ
Single-ended Measurement Points for Delta Cross Point
Differential Measurement Points for Duty Cycle/Period
VMAX = 1.15V nQ VCROSS_MAX = 550mV VCROSS_MIN = 250mV Q VMIN = -0.30V
Single-ended Measurement Points for Absolute Cross Point/Swing
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Application Information
Recommendations for Unused Input and Output Pins Inputs:
LVCMOS Control Pins
All control pins has internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOSOutput All unused LVCMOS output can be left floating. There should be no trace attached.
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Recommended Termination
Figure 1A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50 impedance.
Figure 1A. Recommended Termination
Figure 1B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50 impedance.
Figure 1B. Recommended Termination
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Power Considerations (HCSL Outputs)
This section provides information on power dissipation and junction temperature for the ICS8512061I. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8512061I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VDD_MAX * IDD_MAX= 3.6V *20mA = 72mW Power (outputs)MAX = 46.8mW/Loaded Output pair
Total Power_MAX = 72mW + 46.8mW = 118.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5C/W per Table 5A below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.119W * 129.5C/W = 100.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 5A. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5 2.5 123.5
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3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 2.
VDD
IOUT = 17mA
VOUT RREF =
475 1%
RL 50
IC
Figure 2. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX - VOUT) * IOUT, since VOUT - IOUT * RL = (VDD_MAX - IOUT * RL) * IOUT = (3.6V - 17mA * 50) * 17mA
Total Power Dissipation per output pair = 46.8mW
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Power Considerations (LVCMOS Outputs)
This section provides information on power dissipation and junction temperature for the ICS8512061I. Equations and example calculations are also provided. 1. Power Dissipation.
The total power dissipation for the ICS8512061I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. * * * Power (core)MAX = VDD_MAX * IDD_MAX= 3.6V *20mA = 72mW Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.6V / [2 * (50 + 20)] = 25.7mA Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (25.7mA)2 = 13.2mW per output
Dynamic Power Dissipation at 250MHz Power (250MHz) = CPD * Frequency * (VDD)2 = 8pF * 250MHz * (3.6V)2 = 25.9mW per output
Total Power = Power (core)MAX + Power (ROUT) + Power (250MHz) = 72mW + 13.2mW + 25.9mW = 111.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5C/W per Table 5B below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.111W *129.5C/W = 99.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 5B. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5 2.5 123.5
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Reliability Information
Table 6. JA vs. Air Flow Table for a 8 Lead TSSOP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5 2.5 123.5
Transistor Count
The transistor count for ICS8512061I is: 294
Package Outline and Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP Table 7. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 8. Ordering Information
Part/Order Number 8512061AGILF 8512061AGILFT Marking 61AIL 61AIL Package "Lead-Free" 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev B Table T3C Page 3 Description of Change Added Differential DC Characteristics Table. Date 11/19/08
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Contact Information:
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Corporate Headquarters
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(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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